ISDCS 2018
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The workshop on Power Efficient Design will be held to provide specific emphasis on the emerging application of devices, circuits and Systems.

The list of eminent speakers :


   Talk: An exploration of energy efficiency policies, measures and environmental implications for India

   Speaker: Prof. Tirthankar Nag, PhD, IMI Kolkata




Talk: Effective Power System Operation by using Supply-demand Manager

Speaker: Prof. Yutaka Sasaki, Hiroshima University, Japan (#78)




Talk: Compact Modeling Applicable for Power Efficient Circuit Design (#42)

Speaker: Prof. M. Miura-Mattauschà, Hiroshima University, Japan




Talk: An Overview of High Voltage LDMOS Compact Modeling

Speaker: Prof. Amal B. Bhattacharyya, IIT Delhi



Talk: Stress incorporation in nano-scale metal-oxide-semiconductor field effect transistor channels for controlled performance enhancement

Speaker: Prof.Sanatan Chattopadhyay, Department of Electronic Science, University of Calcutta





Talk: Switched Mode Power Conversion

Speaker: Prof. Mainank Sengupta, EE Department, IIEST Shibpur





Talk: Modeling the 2D flatland: New Paradigm for Nanoelectronics

Speaker: Prof.Amretashis Sengupta, School of VLSI Technology, IIEST Shibpur





Talk: Dual-k Spacer Engineered FinFETs for High Performance Low Power (HPLP) Memory

Speaker: Prof. Sudeb Dasgupta, Microelectronics & VLSI Group, ECE Department, Indian Institute of Technology Roorkee






Talk: A Step Towards On-Chip Optical Communication Through Ultra Sensitive And Power Efficient Photo Detection

Speaker: Partha Sarathi Gupta, School of VLSI Technology, IIEST Shibpur



Talk: Advanced Techniques for Ultra-Low-Power Chip Design

Speaker: Sabyasachi Nag, Azventa Technologies Pvt. Ltd., Bangalore, Email:






Important Dates

Submission deadline:
December 31st, 2017
January 29th, 2018

Notification of acceptance:

February 23rd, 2018

Camera Ready submission:

5th March , 2018


30-31st March, 2018


29th  March, 2018


Click here for registration