|Prof. Sudeb Dasgupta, Microelectronics & VLSI Group, IIT Roorkee|
|Title: Negative Capacitance FETs: A possible Low Power Digital Logic Design Solution to overcome Boltzmann Tyranny
Ultra-low voltage operation is the necessary requirement for today’s requirement of ULP applications. Applications such as Wireless Sensor Nodes and its applications on aIoT platform, neuromorphic computing, security and artificial intelligence requires the ultra-low power systems which can be designed only with the higher Ion/Ioff current characteristic and better sub-threshold slope. Negative Capacitance FETs is one of the possible ways of overcoming the Boltzmann’s subthreshold tyranny of 60mV/decade. The NC FETs with the ferroelectric layer of doped HfO2 is a promising and compatible oxide layer with the CMOS process.In this way, several researchers have demonstrated the different aspects NCFETs in the simulations as well as in the fabrications. In this talk we are going to discuss the physics of negative capacitance FET. The Landau double energy well theory will also be discussed in the perspective of negative capacitance. The implications of landau theory on the planar and non-planar FETs with two different architectures (a) Metal Ferro Insulator Semiconductor (MFIS). (b) Metal Ferro Metal Insulator Semiconductor (MFMIS) will be underlined and appreciated. The applications of NC FETs over the digital logic and different aspects of the polarization switching will also be the part of this talk.
S. Dasgupta, is presently working as a Professor and Head, in the Department of Electronics and Communication Engineering at Indian Institute of Technology, Roorkee. He received his PhD degree in Electronics Engineering from IIT-Banaras Hindu University, Varanasi in 2000. During his PhD work, he carried out research in the area of effects of ionizing radiation on MOSFET. Subsequently, he was member of faculty of Department of Electronics Engg.,at Indian School of Mines, Dhanbad (IIT-Dhanbad). In 2006, he joined as an Assistant Professor in the Department of Electronics and Communication Engineering at Indian Institute of Technology, Roorkee. He is currently the Departmental Chair. He has authored/co-authored more than 250 research papers in peer reviewed international journals and conferences. He is a member of EDS, ISTE and associate member of Institute of Nanotechnology, UK. He has been a technical committee member International Conference on Micro-to-Nano, 2006; and has been acting as an expert member of The Global Open University, The Netherlands. He was awarded with Erasmus Mundus Fellowship of European Union in the year 2010 to work in the area of RDF at Politecnico Di Torino, Italy. He is the recipient of prestigious IUSSTF to work in the area of SRAM testing at University of Wisconsin at Madison, USA in the year 2011-12. He was also awarded with DAAD Fellowship to work on Analog Design using Reconfigurable Logic at TU, Dresden, Germany in the year 2013. His areas of interest are Nanoelectronics, Nanoscale MOSFET modeling and simulation, Design and Development of low power novel devices, FinFET based Memory Design, Emerging Devices in Analog Design and Design and development of reconfigurable logic. He has guided 16 Ph.D scholars. Currently he is supervising around 6 candidates leading to their Ph.D degree. He has been nominated for INAE, Young Engineer Award. Dr. Dasgupta acted as a reviewer for IEEE Transactions on Electron Devices, IEEE Electron Device Letters, IEEE Transactions on Nanotechnology, Superlattice and Microstructures, International Journal of Electronics, Semiconductor Science and Technology, Nanotechnology, IEEE Transactions on VLSI Systems, Microelectronic Engineering, Microelectronic Reliability amongst other. He has also been member of technical committees of various international conferences. He has presented tutorial in VDAT-2014 and VLSI Design Conference, Bangalore 2015 amongst many others. He is part of TPC as a Track Chair for VLSI-D 2017, 2018 and 2019.