|Title:Carrier Dynamics in Lightly-Doped Resistance Region in Power MOSFETs
Two-dimensional current flow in the lightly-doped (LD) resistive region in LDMOS devices was analyzed through 2D device simulation. While retaining the backbone of HiSIM_HV, a conceptual extension is explored. The accumulation region in the LD region adjacent to the channel of the intrinsic MOSFET part is regarded as an extended channel rather than an extended drain. This channel offset length (ΔL) can be expressed within the framework of drift-diffusion model. ΔL can be related with a characteristic quasi-Fermi voltage Vdive where accumulation current flowlines have already completely dived from the surface. An internal drain node (DP) is placed at an opening bounded by the transverse and the lateral extension of depletion region, while many compact models place DP at the boundary between the channel and the LD region. The intrinsic MOSFET’s effective drain voltage (Vdseff) is related to Vdive rather than Vdp. Hence, a difficulty in the intrinsic MOSFET’s drain voltage in the off-state is expected to be removed.
Takahiro IIZUKA received the Ph. D. degree from Hiroshima University, Higashi-Hiroshima, Japan, in 2013. From 1986 to 2012, he was with NEC Corporation, NEC Electronics Corporation, and Renesas Electronics Corporation, where he was involved in carrier transport modeling for TCAD and led a SPICE modeling team during 2003 – 2012. During these years, he was also with Semiconductor Technology Academic Research Center, Yokohama, Japan, where he was involved with the development of the HiSIM family models interacting with Hiroshima University as visiting researcher. Since 2012, he has been with the HiSIM Research Center, Hiroshima University, where he is involved in compact modeling, including maintaining, improving, and developing the HiSIM family models.Dr. Iizuka is a member of IEEE, IEICE (The Institute of Electronics, Information and Communication Engineers, Japan), and JSAP (The Japan Society of Applied Physics), respectively.