|Prof. R. S. Gupta
Maharaja Agrasen Institute of Technology,
Guru Govind Singh Indraprasth University, Delhi, India
Chairperson-IEEE Electron Device Society Delhi Chapter, India
|Title: Modeling and Simulation of Gate-All-Around Junctionless Transistor for High Reliability and Digital Circuit Applications
Continuous market demand motivates device engineers to make Integrated Circuits (ICs) which are area efficient and low power dissipated with reduced fabrication complexity. Integrated circuit industry has shown a lot of technological progress since past few decades. The Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is a central component of IC. Scaling is the major factor behind it. It has attracted many possibilities of novel structures. But scaling poses many challenges as it enters into the nanometer regime. In short channel device, the fabrication complexity also increases as it becomes difficult to form a steep source/drain to channel junctions. To survive future design, fundamental device level changes become mandatory. Recently Junctionless Nanowire Transistor (JNT) has been introduced as the substitute of the junction based transistor. It is uniformly heavily doped throughout the source, channel and drain regions and thus there is no formation of junctions. ITRS mentions reliability as one of the “Design Technology Challenges”. This presentation will discuss briefly on, implications of hot carrier/stress/process/radiation damage induced localised charges on performance of JNT at device and circuit level are studied. Some new techniques are required in order to reduce these reliability issues. In this direction, JNT with vacuum dielectric is also presented as a suitable replacement for SiO2/Al2O3 dielectric to have immunity against hot carriers. The origin of hot-carrier phenomenon is the large longitudinal electric field near the drain end. The greatest control over hot-carrier effects is exerted by minimizing this longitudinal electric field. Electric field at the drain end is found to be much lower in case of vacuum dielectric. For the digital performance, junctionless twin gate transistor has been proposed which has two independent gates. This provides two threshold voltages on a single silicon channel. The full functionality of “NAND” gate circuit is achieved by using only one twin gate transistor.
Prof. R. S. Gupta received Ph.D degree in electronic engineering from the Indian Institute of Technology, Banaras Hindu University, Varanasi, India, in 1970. He joined University of Delhi in 1971. In 1987, he joined Department of Electronic Science, University of Delhi South Campus, New Delhi, India as a reader and later as a Professor from 1997 to 2008. From 2008 to 2010, he served as CSIR Emeritus Scientist. Currently he is Professor with Maharaja Agrasen Institute of Technology, Delhi, India. He has supervised more than 60 Ph.D students. He heads several major research projects sponsered by the ministry of Defence, the Department of Science and Technology, the Council of Science and the Industrial Research (CSIR) and University Grant Commision (UGC), India. He has authored or coauthored more than 700 technical paper published in international and national journals and conference proceedings. The Delhi Chapter of IEE Electron Devices Society, was formed on January 30, 2007 with prof. R. S. Gupta as its founder chairman. His work is well recognized among the leading groups in the field of micro and nano eletronics. His current research interests include modeling and simulation of MOSFETs, MESFETs, and HEMTs for microwave-frequency applications.